vcc1 vcc1 gnd1 gnd1 tp1 tp5 tp2 lo fault clear hi fault clear lo fault hi fault hi 4707 dey road liverpool, n.y. 13088 (315) 701-6751 m.s.kennedy corp. 4900 600v isolated half bridge gate driver features: floating channels up to 600v up to 8 amp peak source and sink current de-saturation protection/shutdown individual on, off and soft shutdown pins for each igbt gate simultaneous conduction lockout contact msk for mil-prf-38534 qualification status mil-prf-38534 and 38535 certified facility description: the msk 4900 is a complete isolated half bridge gate driver hybrid capable of working to 600v channel isolation and 8 amps peak turn-on and turn-off current. housed in an isolated, convenient bolt-down hermetic package, the msk 4900 houses the entire isolated dc-dc converter circuitry and opto-isolators for logic signals. the input logic prevents simulta- neous conduction by locking out both high side and low side drives in case both inputs are asserted on at the same time. each gate drive is capable of sourcing and sinking up to 8 amps peak current. the turn-on and turn-off pins are separate to allow separate gate current control. upon detection of a de-saturation condition, a fault is presented and the transistor is shutdown by a separate controlled shutdown pin. there are two modes available for clearing a fault. they are selected at device power up. manual fault clear mode requires the fault to be cleared by the system before normal operation will begin again. automatic fault clear mode clears the fault a short period after shutdown at which time normal operation commences. the msk 4900 has good thermal conductivity due to an isolated substrate/package design that allows direct heat sinking of the device without insulators. equivalent schematic typical applications inverter bridge gate drive motor control bridge gate drive 1 pin-out information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 tp4 tp3 lo nc vcc2 vcc2 gnd2 gnd2 gnd2 nc nc nc 25 26 27 28 29 30 31 32 33 34 35 36 nc nc nc nc soft shutdown lo lo off lo vss lo on lo vdd return lo de-sat sense lo nc 37 38 39 40 41 42 43 soft shutdown hi hi off hi vss hi on hi vdd return hi de-sat sense hi 8548-32 rev. j 8/13
typ. 15.00 300 500 660 - - 0.15 - 16.25 -5.0 - - 25 3.1 3.1 1.25 1.25 10.4 7.4 0.44 0.175 0.175 vcc supply characteristics vcc voltage vcc quiescent current vcc operating current vcc operating current input/output logic positive trigger input voltage negative trigger input voltage open collector ouput - vol open collector ouput - iol output characteristics - gate drive voh vol ioh peak iol peak soft shutdown time tplh - propagation delay time tphl - propagation delay time tr - rise time tf - fall time td - de-sat delay time de-sat trip voltage r ds(on) xon r ds(on) xoff r ds(on) ssox 600v 5.5v 15.75v 90ma 8a 17c/w 10ma high voltage isolation logic input voltage vcc supply continuous output current peak ouput current thermal resistance (output drivers - junction to case) maximum current sink-open collectors v ma ma ma v v v ma v v a a s s s s s s v absolute maximum ratings -65c to +150c +300c -40c to +85c -40c to +125c +150c t st t ld t c t j parameter electrical specifications units max. 15.75 350 575 770 - 0.8 0.4 1.5 17.5 4.4 - - 30 4.0 3.5 1.75 1.75 11.5 8.5 - - - msk 4900 typ. 15.00 300 500 660 - - 0.15 - 16.25 -5.0 - - 25 3.1 3.1 1.25 1.25 10.4 7.4 0.44 0.175 0.175 test conditions min. 14.25 250 425 550 2.0 - - - 15.0 -5.75 8 8 20 2.5 2.5 0.75 0.75 9.5 6.8 - - - storage temperature range lead temperature range (10 seconds) case operating temperature msk4900 msk4900h junction temperature all ratings: tc=+25c unless otherwise specified 2 max. 15.75 350 575 770 - 0.8 0.4 1.5 17.5 4.4 - - 30 4.0 3.5 1.75 1.75 11.5 8.5 - - - msk 4900h min. 14.25 250 425 550 2.0 - - - 15.0 -5.75 8 8 20 2.5 2.5 0.75 0.75 9.5 6.8 - - - group a subgroup no pwm c l =0.22 f, 20khz 1 channel c l =0.22 f, 20khz 2 channel 6 i ol =1.5ma c l =0.22 f, 20khz pulse - 1 1 1 7 1 7 1 7 - 1,2,3 1,2,3 1,2,3 - - - - - 1,2,3 1,2,3 - - 4,5,6 4,5,6 4,5,6 4,5,6 4,5,6 4,5,6 4,5,6 - - - 8 1 1 1 1 9 8548-32 rev. j 8/13 10 notes: guaranteed by design but not tested. typical parameters are representative of actual device performance but are for reference only. industrial grade devices shall be tested to subgroups 1 and 4 unless otherwise specified. military grade devices ("h" suffix) shall be 100% tested to subgroups 1, 2, 3 and 4. subgroups 5 and 6 testing available upon request. subgroup 1, 4 t a = t c = +25c 2, 5 t a = t c = +125c 3, 6 t a = t c = -40c continuous operation at or above absolute maximum ratings may adversly effect the device performance and/or life cycle. x=hi or lo all tests performed using msk 4900 test circuit unless otherwise specified. when applying power to the device, apply the low voltage followed by the high voltage or alternatively, apply both at th e same time. do not apply high voltage without low voltage present. internal solder reflow temperature is 180c, do not exceed. 1 2 3 4 5 6 7 8 9 10
application notes in msk 4900 pin descriptions 3 vcc1,2 - are the bias supply voltages for supplying the input logic and the power supply for the isolated output. these pins should be by- passed to gnd with a 22 f tantalum capacitor and a 0.1 f ceramic capacitor as close to the pins and gnds as possible. the connected power supply must be able to provide a minimum of 1amp to satisfy the internal dc-dc converters in rush current at power up. latch up will occur if the supply current isn't adequate and the device will not function. gnd1,2 - are the vcc supply returns for the input logic and the inter- nal isolated supply. these gnds are completely isolated from the output section. no output returns should connect to these gnds in order to preserve isolation. all vcc bias supply bypass connections should be made as close to these pins as possible. an input ground plane is the most preferred layout for assuring good, low impedance ground, shielding of inputs from noise, etc. hi - is the input logic pin for commanding the high-side gate drive to turn on. this logic input is ttl compatible. this input is exclusive or'd with lo to protect against simultaneous turn on of both the high- side and low-side gate drive. there is no dead-time programmed be- tween hi and lo activation. lo - is the input logic pin for commanding the low-side gate drive to turn on. this logic input is ttl compatible. this input is exclusive or'd with hi to protect against simultaneous turn on of both the high- side and low-side gate drive. there is no dead-time programmed be- tween hi and lo activation. note: x = hi or lo x fault - is an open collector output for indicating a de-saturation condition for the gate drive. this output will be cleared upon activation of x fault clear. x fault clear - is a logic input pin for clearing a fault condition in manual fault clear mode. the mode is determined by the logic level seen on this pin at device power up. to set manual fault clear mode the pin must be held at logic high during power up. to set automatic fault clear mode the pin must be at logic low during power up. in manual mode a fault is cleared by driving the pin to logic low and back to logic high. allow 30usec after fault before activation of this pin. once this pin is activated and released (10usec min.), normal operation will commence. in automatic mode this pin is ignored and should be connected to ground. after any fault occurs it is cleared 150usec after shutdown completes allowing normal operation to continue. x on - is the gate drive output pin for turning the gate on. this pin will source 90ma continuous, 8a peak current. a separate gate resistor shall be selected to tailor the turn-on characteristics. this pin will turn on to +15v. x off - is the gate drive output pin for turning the gate off. this pin will sink 90ma continuous, 8a peak current. a separate gate resistor shall be selected to tailor the turn-off characteristics. this pin will turn off to -5v. de-sat sense x - is the input connection for sensing de-saturation. the de-sat voltage is with respect to return x. it is necessary to include a reverse-biased zener diode and a reverse-biased schottky diode between de-sat sense x and return x, along with 100 series resistor and an ultra fast recovery diode (600v) to protect against high voltage at the de-sat sense x pins. this circuitry will protect against positive voltage spikes greater then the de-saturation voltage, and negative voltage spikes with respect to return x. in many cir- cumstances, pwm switching of other transistors in the power stage can cause switching spikes to inadvertently trip the de-saturation cir- cuitry, causing false faults. this pin (through the protection diode circuit) shall be connected directly to the collector of the igbt being sensed by a separator wire connection. this pin is blanked during switching so that it will not false trip, and will be blanked internally for 5usec after gate drive turn-on. x vdd - is the pin for the floating gate supply voltage. 47 f of bulk capacitance and 0.1 f high frequency capacitance shall be connected between this pin and x vss as close to the pin as possible. nomi- nally, this voltage will be +15v with respect to the return x pin and the emitter of the igbt. x vss - is the return pin for the floating gate supply voltage. 47 f of bulk capacitance and 0.1 f high frequency capacitance shall be con- nected between this pin and x vdd as close to the pins as possible. nominally, this voltage will be -5v with respect to the return x pin and the emitter. ssd x - is the soft shutdown pin for slowly turning the gate off after a de-saturation condition. this pin is a separate gate turn-off path and requires a separate gate resistor for this special turn-off ap- proach. the resistor should be sized to keep di/dt from being too high after the de-sat condition. once de-sat is detected, 25 s of soft shutdown turn-off will occur. after that, soft shutdown will de-acti- vate and x off will turn on until x fault clear is activated and released. return x - is the pin for the emitter reference to the igbt being driven. this pin will be at zero volts to +15v to -5v for the gate drive voltage. this pin shall include the de-sat diode circuitry and shall be connected directly to the emitter of the igbt by a separate wire connection. operation +15v must be applied at least 65msec before the system high voltage is applied. the internal processor will be initialized 64msec after +15v. during the 64msec, hi, lo must be pulled logic low and x fault clear must be held logic high to select manual fault clear mode or held logic low to select automatic fault clear mode. once hi/lo is pulled logic high, hi or lo (respectively) gate drive will turn on, providing +15v gate drive to the igbt. de-satura- tion sensing will be blanked for 5 sec to allow switching transients to settle. after 5 sec, de-sat sense x will be active. if de-satura- tion occurs, an additional delay of 5usec due to a digital noise filter function occurs then the x hi or x lo gate drive will turn off and soft shutdown - ssd x will turn-on, slowly turning the offending igbt off to avoid excessive dv/dt and di/dt during this time. x fault output will also be triggered, telling the system that a de-sat shutdown occured. soft shutdown will continue for 25 sec, after which ssd x pin will turn off and the normal x off pin turn on, holding the igbt gate off until x fault clear gets cycled low then high by the system if manual fault clear mode has been selected or for a period of 150usec if automatic fault clear mode has been selected. once cleared, normal operation will begin again. hi and lo will turn on and off their approprate igbt's, but will not turn them on simultaneously. the processor exclusive or's the inputs to prevent this condition. one input is not master of the other. if both are on, the processor will shut both off until the condition is removed. there is no built in dead-time between hi and lo. it is up to the system to provide adequate dead-time to prevent igbt shoot-through. the minimum hi and lo pulse width is 1.5 sec. this is for both duty cycles approaching 0% and approaching 100% due to program propa- gation time. this means that any pulse input to hi and lo pins will be interpreted as a 1.5 sec pulse until the actual input pulse width extends past 1.5 sec or 0% duty cycle is reached. for duty cycles approaching 100%, any pulse high going low with a width of less than 1.5 sec will be interpreted as 1.5 sec going low pulse until the pulse width going low becomes greater than 1.5 sec, or 100% duty cycle is reached. note: tp pins 5,6,7,13,14 - are for factory use only. they are used dur- ing manufacturing for programming and test purposes only. leave these pins unconnected. 8548-32 rev. j 8/13
typical application 4 8548-32 rev. j 8/13
msk4900 test circuit 5 8548-32 rev. j 8/13
the information contained herein is believed to be accurate at the time of printing. msk reserves the right to make changes to its products or specifications without notice, however, and assumes no liability for the use of its products. please visit our website for the most recent revision of this datasheet. contact msk for mil-prf-38534 qualification status. mechanical specifications m.s. kennedy corp. 4707 dey road, liverpool, new york 13088 phone (315) 701-6751 fax (315) 701-6752 www.mskennedy.com 6 ordering information note: all dimensions are 0.010 inches unless otherwise labeled. esd triangle indicates pin 1. weight= 88 grams typical the above example is a military grade hybrid with leads bent up. msk4900 h u lead configuration s=straight, u=bent up, d=bent down screening blank=industrial; h=mil-prf-38534 class h general part number 8548-32 rev. j 8/13
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